Digital IC Designer

VEBV01657

Your mission

As a digital IC design engineer you develop low power SRAM from specification development until production for the low power technology market. You work closely together with the silicon architect to agree on product specifications. Your tasks:

  • Transistor level design, simulation and layout
  • Development of layout and verification flows
  • Design margin analysis and guard band provision
  • Simulate data- and high sigma statistical analysis
  • Design methodology development & optimization
  • Layout verification (DRC & LVS)
  • Identification of patentable circuit/architectural design features

Your experience

  • Master in Engineering (electronics)
  • At least 3 years of experience in digital IC design, SRAM design
  • Good knowledge of Python or strong scripting skills
  • Profound Knowlegde of EDA tools (Cadence/Mentor)
  • Experience in SRAM verification, low power compiler design & advanced FinFET nodes
  • Good understanding of SRAM structure and issues
  • Good knowledge of DFT, yield and DFM issues
  • Strong analytical and problem-solving skills
  • Fluent in English

VeroTech offers you

  • Grow your talents by challenging mid to long-term R&D projects in different industries
  • Join an inspiring community of engineers with different backgrounds and seniority levels
  • Working in a people-oriented company with an informal working environment
  • Close follow-up of your career path combined with technical and business related trainings
  • A motivating salary, with extralegal benefits and the possibility of a company car

Location

Leuven

Publication date

04-04-2019