Senior Digital IC Designer


Your mission

As a Digital IC Designer 5G, you work on new wireless technologies. You are responsible for the design of a single IP or the full digital toplevel af transceiver chips. Your tasks include:

  • Define the block level architecture, taken into account the design constraints and run synthesis
  • Design analog/RF blocks, digital blocks and software running on the processor
  • Implement the design in Verilog
  • Write block level testbenches for debugging purposes
  • Support other teams (characterisation, verification, back-end)

Your experience

  • Master in Engineering
  • Minimum 8 years of experience in frond-end digital IC design, from design concept to GDS2
  • Able to set-up and run ASIC analysis and interpret synthesis results
  • Proficient in Verilog, design constraints, STA, RTL lint, Logical equivalence checking
  • Good knowledge of state-of-the-art verification methodologies (SystemVerilog/UVM)
  • Practical know-how of wireless communication chips or implementing signal processing algorithms is an asset
  • Knowledge of common on-chip bus protocols
  • Fluent in English

VeroTech offers you

  • Grow your talents by challenging mid to long-term R&D projects in different industries
  • Join an inspiring community of engineers with different backgrounds and seniority levels
  • Working in a people-oriented company with an informal working environment
  • Close follow-up of your career path combined with technical and business related trainings
  • A motivating salary, with extralegal benefits and the possibility of a company car



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