Senior RF IC Layout Engineer


Your mission

As a Senior RF IC Layout Engineer, you work on new wireless technologies such as 5G. You are responsible for the layout design of high speed analog and RF circuits for the next generation mobile phone chips. Your tasks include:

  • Perform the layout design for new analog IC's
  • Make the floorplanning and optimisation of the system on chip
  • Verify the connectivity and design rules
  • Take into account the constraints from the design and optimise the layout from a performanice and aera perspective
  • Liaise closely with analog designers on specific circuit requirements, e.g. power, sensitivity, etc.
  • Perform extraction of parasitics and make the interpretation of these results for further optimisation
  • Work together with CAD and RF engineer to improve processes or features

Your experience

  • Master or PhD in Engineering (electronics, microelectronics,...)
  • Minimum 5 years of experience in analog RF IC layout in CMOS technology
  • Good know-how of Cadence and Mentor tools on nanometer RF CMOS and/or RF SOI technologies
  • Experienced in RF circuit layout in the sub 10-GHz range
  • Good understanding of different topologies and their constraints for layout
  • Knowlegde of Finfet technology and layout automation is an asset
  • Fluent in English

VeroTech offers you

  • Grow your talents by challenging mid to long-term R&D projects in different industries
  • Join an inspiring community of engineers with different backgrounds and seniority levels
  • Working in a people-oriented company with an informal working environment
  • Close follow-up of your career path combined with technical and business related trainings
  • A motivating salary, with extralegal benefits and the possibility of a company car



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