Cochlear - ASIC/FPGA development at Cochlear Technology Center, Mechelen
The client
Cochlear is a global leader in implantable hearing devices. The company has provided hearing implants to more than 600 000 people, helping them to hear and connect with life’s opportunities. They produce several types of implantable devices carefully designed to help user’s specific hearing needs. To meet their goal of improving and revolutionizing implantable hearing solutions, Cochlear invests in lots of R&D. Their largest Technology Center outside of Australia, is located in Mechelen, Belgium.
The figure above illustrates what a typical hearing implant looks like. Cochlear implants consist of four subsystems that work together. The subsystems can be broadly divided into the internal implant (2,3,4) and the sound processor (1) which remains outside of the body. Both systems communicate wirelessly through radio frequency, magnetic induction, etc. Some of the advanced products even have the possibility to interact with accessories through Bluetooth.
One of the challenges with these implantable hearing solutions is that they include lots of electronic components and software algorithms, which making them high in energy consumption . To increase the durability of the devices, Cochlear is looking into ways to lower the power consumption of the system’s electronic IC’s and processors by developing their own ASICs. These will go into internal implant as well as external sound processor. Some of Cochlear’s current ASICs are purely analog ICs , some are digital ICs but the bigger part of the ASICs developed by Cochlear are mixed signal ICs.
The added value of our consultant
Reniflal, senior electronics consultant
Reniflal joined Cochlear Technology Center as ASIC Consultant through VeroTech in January 2022. He is consulting on a platform project which consists of several ASICs. Over the course of 1.5 years, Reniflal has been working with Cochlear on the verification of a proprietary ASIC IP and on the architecture of FPGAs which will be used for verification and qualification of different ASICs that will go into Cochlear’s next generation hearing implant solutions.
His verification work involves working on a testing plan and using python to implement tests which interact with the hardware setup and ASICs to make sure that the requirements are met. It also involves reviewing implementations from suppliers and supporting suppliers on bug fixing. Refinlal’s FPGA architecture work involves interacting with different Cochlear product owners to understand the requirements needed for the FPGA, document them using requirement capture tools and communicating with suppliers on the requirements and implementation. This especially requires a lot of co-ordination with different teams.