Space ASIC: why a chip that works isn’t a chip that’s flight-ready.

No reset. No technician. A decade in space. To make your design more compact, efficient and more competitive, you decide to integrate a part of it into an ASIC (Application-Specific Integrated Circuit): a custom-built chip designed to perform a specific task. 

But what does it take to get from this idea to a complex semiconductor device that is ready to be mounted into flight equipment? It needs to be designed to function reliably when exposed to radiation, temperature extremes, manufacturing variations and years of operation, in an environment where there is no possibility of repair.

Architecture and technology: the first trade-off

First, you need to clearly define your requirements and come up with an architecture for the ASIC. This will define the type of technology that will be used. In space applications, these choices involve significant trade-offs. Smaller and more efficient transistors may offer performance and power advantages, but they are more sensitive to single event effects. Larger transistors are more susceptible to total ionizing dose. The amount of radiation a component sees in its lifetime is also very mission dependent, as radiation is more concentrated in some zones around Earth. A mission to the Moon, for example, will often see less radiation than some satellites staying in orbit.

Design and verification

When the architecture and technology for the ASIC is defined, it is time to start on the detailed design, which also includes the choice of the package and needs to take into account manufacturing processes and heat dissipation. Thermal management is particularly challenging in space: there is no convection, so heat must be conducted out through the package and the board to a radiator.

To make sure the design works as intended, simulation becomes a major part of the process. For space, these simulations are even more thorough. The safety margins are bigger and each corner case is tested, even if the chance of occurrence is extremely small. Any small design change requires another manufacturing cycle, with implications for time and cost. The extent of these implications depends on which production steps need to be modified and how many are affected. Costs can range from around ten thousand euros, with a delay of a few months for a redesign limited to a single metal layer, to several million euros and delays of up to two years for a complete chip redesign. That makes simulation and verification critical. But even extensive simulation cannot eliminate all uncertainty. And that is where testing becomes essential.

Testing starts before the chip exists

To reliably test an ASIC, an ATE (automated test equipment) is used. Developing the test system happens at almost the same time as developing the ASIC itself. Starting without any 'known good' components makes it hard to tell whether you are looking at a bad test or a bad device. Testability must therefore be considered alongside the design itself, with choices such as Design for Test (DFT), scan chains and Built-In Self-Test (BIST) already being made during the architecture phase.

The first iteration or prototype of a new design is often on a MPW (multi-project wafer). This allows for a low-cost, low-volume production run, enabling the physical chip to be tested before moving to full-scale production. These prototype chips could also be used to help develop the test setup.

Once you have made a test setup that can reliably filter good from bad samples and you have defined your production tolerances, you can use this setup to start your qualification campaign.

Qualification: from environmental stress to proven reliability

Qualifying components for flight in space is quite an extensive process. Space components need to withstand a range of environmental stresses, with qualification campaigns often based on standards such as ECSS-9000 (European space standards) or MIL (American military standards), or combinations of both. A qualification campaign can easily take one to two years and the number of individual measurements reaches hundreds of thousands.

Qualification tests include temperature extremes, humidity, electrostatic discharge and ageing. And specifically for space applications, radiation (Total Ionizing Dose (TID) and single events) is one of the most important additional considerations. 

When you need more components and start a new production batch, the new wafer lot must undergo lot acceptance testing (LAT) and radiation lot acceptance testing (RLAT) to verify that it meets the required specifications. There is no guarantee that a new production batch behaves the same, even though the design has not changed.

This illustrates a fundamental reality of space electronics: reliability is not something you establish once and forget about. It must be continuously demonstrated.

From functionality to confidence

Developing an ASIC for space applications is a long and demanding journey that extends far beyond the chip design itself. First, you need confidence in the architecture and technology; then in the design; then in the manufactured devices; then in the test process; finally, you need confidence that the qualified component can withstand the environment in which it will operate. Each step adds another layer of verification, because confidence in one stage does not automatically guarantee reliability in the next.

That is what makes a flight-ready ASIC fundamentally different from a chip that simply works. Confidence in the architecture doesn’t guarantee confidence in the design, and a working design doesn’t guarantee a reliable device once it’s in orbit. Every step needs its own proof. In space, there is no reset button, no technician to swap a component and often no second chance. The real engineering challenge is building enough confidence in every step of its journey to trust it when it finally leaves Earth.

Working on an ASIC for space?

Not every team has the right experience in-house at the right moment. If you’re considering an ASIC, or you’re already mid-project, we can reinforce your team where it matters most: developing the test system, verifying the design or running the qualification campaign.  Get in touch and we’ll look together at what profile your project needs.

Want to be the engineer who makes sure a chip is ready before it leaves Earth? See our open vacancies at careers.verotech.be.